ATA8743-PXQW【PDF 62/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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9152BINDCO02/10

ATA8743

16.4 Register Description

16.4.1

MCUSR MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU Reset.

" Bits 7..4 Res: Reserved Bits

These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.

" Bit 3 WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

" Bit 2 BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

" Bit 1 EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

" Bit 0 PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then reset

the MCUSR as early as possible in the program. If the register is cleared before another reset

occurs, the source of the reset can be found by examining the Reset Flags.

16.4.2

WDTCSR Watchdog Timer Control and Status Register

" Bit 7 WDIF: Watchdog Timeout Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-

ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt

handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in

SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

" Bit 6 WDIE: Watchdog Timeout Interrupt Enable

When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the

Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed

instead of a reset if a timeout in the Watchdog Timer occurs.

If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful

for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared,

Bit

0x34 (0x54)

WDRF

BORF

EXTRF

PORF

MCUSR

Read/Write

R/W

Initial Value

See Bit Description

Bit

0x21 (0x41)

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

WDTCSR

Read/Write

R/W

Initial Value

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